Tier IV has joined the Next-Generation Edge AI Semiconductor Research and Development Program led by Japan’s Science and Technology Agency (JST) to develop a software-defined system-on-chip (SoC) for Level 4 autonomous driving. The company plans to open-source the chip’s logic design, along with its compiler and toolchain, once development is complete.

Under the JST programme, a research team led by Professor Yoshihiro Kawahara of the University of Tokyo will study use-case-driven, functionally differentiated chip design for physical AI applications. Tier IV, meanwhile, is developing the logic design for a chip intended to process inference for end-to-end autonomous driving AI.

SoC software and hardware architecture

Rather than focusing solely on peak performance, Tier IV aims to improve performance per watt across the autonomous driving system, including Autoware. The design will use the Tensor Operator Set Architecture (TOSA), a standardised intermediate representation that decouples AI models from hardware, allowing updates through software rather than a full chip redesign.

Tier IV will also introduce formal verification techniques to confirm the numerical consistency of AI model transformations before and after compilation, addressing the reliability demands of safety-critical Level 4 systems. Founder and Chief Executive Shinpei Kato said the initiative extends Autoware’s open-source philosophy to chip design, building an ecosystem manufacturers and developers can build upon independent of closed products.

Source: Tier IV